\chapter{Conclusions and Future Work}
\section{Conclusions}
How to enhance the observability inside the chips has become
vital for effective Post-Silicon Validation. As have been shown in the
dissertation, we proposed different automated trace signal selection algorithms to help
improve the observerbility of the chips when using ELA-based debugging
infrastructure. Our algorithms showed considerablly better solution
quality and scalability over a set of algorithms proposed to maximize
the state restoration. Still, lots of work needs to be done to
further improve visibility and better utilize the restored data to
locate the bugs. Meanwhile, there are emerging thoughts that the trace buffer may
be directly used for Electrical bugs detection, such as incorporated in
the critical-path based anyalsis. We now summarize the potential
paths for future researches on trace-buffer based PSV as follows.

\section{Future Research Direction}
\subsection{Improving Trace Signal Selection Algorithms}
So far, algorithms have been focusing on maximizing the State Restoration
Ratio (SRR), which is defined for general debugging purpose. However, we observed
that this metric may not be useful in some cases. For example, state
elements whose outputs switch infrequently
may be traced, resulting in the restoration of other infreqently swiched
state elements. This may not be good for bug detection since it does not
obey the error propagation mechanism. In another case where limited
on-chip tracing can not acheive high SRR, greedy selection strategy will 
try to maximize the restoration by selecting traces within a small region, 
resulting in poor or no visibility to
the remaining part of the circuit (work in \cite{ChatterjeeMB11} used a
backward elimination selection strategy which may not lead to this
situation. However, the runtime complexity of the algorithm is too high for
large benchmarks). These two issues expose two potential research
directions regarding finding new objectives to optimize and applying new
strategies for selection. 

The first option will be to \emph{define better objectives for trace
  selection targeting on specific debugging purposes}. This is also
referred as ``biased selection'' in some references when compared with
the selection strategies of maximizing the SRR. For example, in \cite{YangT12}, the authors
proposed a trace signal selection approach based on the observations of error
propagation in sequential circuits. An ILP formulation is later applied to
identify the state elements that are most sensitive to errors and get traced. 
%However, there are some issues related to the biased selection strategy.
%\begin{itemize}
It should be pointed out that the biased selection is usually used
to assist the detection of certain bug types and should be applied after
bugs have been (coarsely) located. However, few existing works have 
discussed into details about the trace-buffer based debugging flow when
high SRR is unacheivable. For small benchmarks (the ones in ISCAS'89), 
trace signal selection algorithms show that with a buffer width of 32 bits, most
of the state elements can get restored (when interpreting SRR value into the number of state
elements restored, supposing each of them is restored at every cycle). 
But for larger benchmarks (e.g. the IWLS'05 and ISPD'12 benchmarks), we notice that even with a
buffer width of 64 btis, it is hard to restore more than half of the state elements. 

Therefore in our opinion, it is necessary to develope a hierachical
debugging infrastructure to gradually detect and locate the bugs since it is hard to obtain a
comprehensive visibility in the first place. Note that building a hierachical
debugging infrastructure will require help from the manufacturing side as
will be elaborated in the next section, because current ELA infrastructures
have little flexibility and trace signal selection can only be done once, before
the debugging process starts. Specially in the higher hierachies, the goal
of debugging will be to search for potential buggy spots and coarsely
position the bugs. SRR can be one possible objective to optimize at this
point. Then in the lower hierachies, objectives related to detailed debugging purposes need to be optimized, which helps gradually locating the bugs.
%\end{itemize} 

On the other hand, from the algorithmic perspective, current greedy selection schemes
(either forward or backward, also including region-based strategy
\cite{BasuM11}) \emph{lack an overall assessment (budgeting) of the ``restorability'' of
  the circuit} before selection algorithms are applied. This will force the
selection process to be confined to a small portion of the circuit when
high SRR value is unacheivable (of course this is related to the
performance of trace signal selection algorithms). With a guide of the
restorability of the whole circuit, we can better adjust
the emphasize of trace signal selection for different purposes as the selection
process proceeds. More precisely, assessment for different
regions would decide for each region how many signals need to be traced (regarding the
objective). However, it should be pointed out that this
assessment may not be easy to realize. The state restoration process has
a nonlinearly increasing feature in terms of SRR as new signals are selected
\cite{ChatterjeeMB11}. Therefore it could be possible that a big leap of SRR exists for a region
after the addition of a single trace. It thus complicates the problem when
compromising the restoration of one region to boost another if taking these situations into
consideration. 
  
\subsection{Applying 3-D Stacking Manufacturing Techniques on Interconnenction Network Design} 
If not for the limitation of on-chip whitespaces, more signals can be
traced and visibility will be improved. The recent innovation in
manufacturing technology---3D stacking provides a new opportunity \cite{}. A memory
can be placed above the CUD chip thus the routing wires do not need to
take the white spaces of the CUD and there will be much more room
to build a selection network covering most, or even all of the state
elements. Meanwhile, there can be a control unit designed to
control in-time trace set shift. This can add great flexibility to
Post-silicon Validation, as trace signals can be altered during validation
to deal with different bug types. On the other hand, shorter distance
between trace signals and memory can introduce less variations resulted from routing components to the electrical attributes of the CUD.

\subsection{Collaboration with Other Debugging Techniques} 
Other DFD hardwares can also be combined with the trace buffer to improve
the visibility inside the chips. One research along this direction is to combine
scan-chain and trace buffers to improve the SRR \cite{}. 

\subsection{Trace Signal Selection for Detection of Failing Paths}\label{sec:f3} 
Trace signal selection problem has so far been defined
assuming the solution will be used for debugging logic errors. The delay of
each gate is a function of the supply voltage of the gate. Here we propose
to extend the definition of the trace signal selection problem for detecting
failing paths due to timing errors.

For current technologies, the drop in the voltage can significantly
increase the delay of the gates and result in a timing error on a
combinational path in the circuit. At the same time, voltages at
different locations on the chip (for different gates) are highly
workload-dependent \cite{}. So even for the same gate, the voltage can vary at
different times, and different gates can have a different voltage at the
same point in time. Prediction of the voltage droop for a given time and
location can significantly help the debugging process for timing errors however
it is a very difficult problem which requires time-consuming simulation.

Here we propose to define and investigate a variation of trace signal
selection to help debug timing errors which are caused by voltage
droop. Specifically, our goal is to reconstruct a ``voltage droop map'' on
the chip within the observation window. This map specifies the voltage at
each location on the chip at each time step within the observation
window. The delays of the gates can then be adjusted accordingly at each
point of time based on the predicted voltage droop map. The timing behavior
of the paths can then be verified after this delay adjustment and the paths
which are failing the timing constraint can be predicted using this
approach.

The trace signal selection problem has so far targeted restoration of state
elements. However, to construct the voltage droop map, we need to restore
the switching profile of each logic gate within the observation
window. Therefore we define and propose to investigate a variation of the
problem in which restoration of logic gates is also a secondary
objective. Because of the high number of logic gates, we propose to first
focus on the variation in which a subset of potentially-failing paths need
to be monitored. Therefore restoration of the gates on these paths will be
our major concern.

More specifically, we assume the inputs to the problem is a set of
``critical'' gates which need to be restored which are the gates on the
already-specified potentially-failing paths. We then define the problem to
maximize SRR (on state elements) as the primary objective, and the
restoration of the critical gates as the secondary objective. Similar to
SRR, we can define a GRR metric denoting the Gate Restoration Ratio and
define the objective to be a linear combination of SRR and
GRR. Furthermore, the gates on the critical path can be assigned a weight
based on the degree of their criticality so the gates with higher weights
are given a higher priority of restoration by our algorithm. This can be
incorporated by extending the Impact Weight of each state element to
consider the restoration on each critical gate based on its weight. After a
trace solution is found, XSimulation is done to construct the restoration
map which is then used to predict the switching activity of each gate.

\subsection{Design-for-Debug Hardware for Timing Errors} Our preliminary
observations show that the trace buffers may not be the best
design-for-debug hardware for monitoring the necessary quantities for
prediction of timing errors.  For example, when considering timing error
due to power-droop (in Section \ref{sec:f3}), the goal is restoration of
switching activities of the critical gates. However, using trace buffers,
we can only restore individual gates and state elements of the circuit, at
each point of time (by maximizing SRR and GRR). This does not necessarily
mean that the switching activity will be predicted accurately. For example
assume a signal is restored within 90\% of the observation window which can
be considered a high restoration ratio. However, during this restoration
period, the signal may not switch at all while it might have a high rate of
switching during the 10\% of the observation window that it is not
restored. Therefore, the prediction of switching activity may be poor
despite the high restoratability rate for that signal over the entire
observation window.

Therefore, in this section, we propose to investigate new design-for-debug
hardware components in order to generate new signals which explicitly
measure various quantities necessary for debugging of timing errors. For
example, one component can directly measure the switching activity of the
critical gates. The output of this component can be directly traced by the
trace buffer. Specifically, we can record the clock cycle ID whenever the
content of the corresponding state element is flipping.

We also observe that different signals can have significantly different
switching activities and the switching of the state elements happen in
different clock cycles compared to each other. %For example, if a signal
$s_1$ switches more frequently than signal $s_2$, This requires changing
the way the data is written to the on-chip trace buffer. (Previously, at
each cycle the values of each trace signal was written to the trace buffer
however now we require a signal to be recorded only if it is
switching. Therefore the switching information will not be recorded
simultaneously among the trace signals.) In this case, the on-chip buffer
needs to be redesigned to better address these challenges. For example, the
buffer can be partitioned into regions in which each region corresponds to
the switching information for only one of the trace signals.
